With the increase in integration degree of semiconductor devices, field effect transistors such as MISFET (Metal Insulator Semiconductor Field Effect Transistor) are miniaturized in accordance with the scaling law. However, with the miniaturization of the field effect transistors, the short-channel effect appears or the uniformity in threshold voltage is degraded, so that the performance of the semiconductor device is likely to be degraded.
On the other hand, in the MISFET on an SOI substrate in which a BOX (Buried Oxide) layer that is a buried oxide film and an SOI (Silicon On Insulator) layer that is a semiconductor layer are formed on a bulk substrate, the short-channel effect can be easily suppressed and the variations in threshold voltage can be reduced in comparison with the MISFET on a bulk substrate, and the performance of the semiconductor device can be enhanced. For this reason, the MISFET on an SOI substrate is regarded as a technology necessary for realizing the semiconductor device in the generation of the circuit line width of 40 nm or less and the low-power semiconductor device.
Japanese Patent Application Laid-Open Publication No. 2013-191760 (Patent document 1) discloses a technique of forming a field effect transistor on a main surface of a semiconductor substrate made up of a silicon substrate, a BOX layer and an SOI layer in a semiconductor device.
Japanese Patent Application Laid-Open Publication No. 2004-349315 (Patent document 2) discloses a technique of fabricating a strained SOI substrate wafer, in which an oxide film layer, an SiC epitaxial layer and a silicon layer having a lattice strain are sequentially formed on a silicon substrate, by the bond and etch-back method.